The present invention relates to a semiconductor device and an IC card including a semiconductor device, and particularly relates to a semiconductor device including a memory circuit and a voltage supply circuit for supplying a predetermined voltage to the memory circuit, and an IC card including the semiconductor device.
With the recent progress in the semiconductor processing technology, the size of elements of constituting a semiconductor device is reduced and at the same time, the operation voltage of semiconductor devices is reduced. When a chip part formed by the recent processing technology is used for a known electric device, an internal voltage generated by reducing a power supply voltage for the electric device is used in the chip part.
More specifically, in recent years, as for IC cards including a semiconductor memory device, a non-contact IC card which receives by an antenna coil an electromagnetic wave supplied from the outside of the IC card to obtain a power supply voltage has been developed. In such an IC card, it is necessary to supply a stable internal voltage to a nonvolatile memory without depending on a variation in a voltage supplied from the outside. Hereinafter, as a first known example, a semiconductor memory device using a voltage reduction circuit for reducing a power supply voltage to generate an internal voltage will be described.
FIG. 8 is a block diagram illustrating the configuration of a semiconductor memory device according to a first known example. As shown in FIG. 8, a power supply voltage VDD input into a power supply terminal is reduced by a voltage reduction circuit 101 and then supplied as an internal voltage VINT to a logic circuit 102 and a nonvolatile memory 103. When a nonvolatile driving signal NCE output from the logic circuit 102 is the “L” level, the nonvolatile memory 103 is activated to start an operation.
In this case, the voltage reduction circuit 101 includes a p-channel output transistor QP11 having a gate connected to an output terminal of a differential amplifier circuit 111, and the power supply voltage VDD input from the power supply terminal is reduced by the output transistor QP11 to be an internal voltage VINT having a lower potential than that of the power supply voltage VDD.
One input terminal of the differential amplifier circuit 111 is connected to a reference potential generator circuit 112 for generating a reference potential VREF and the other input terminal thereof is connected to a voltage divider circuit 113 for generating an intermediate potential VMID between the internal voltage VINT and a ground voltage VSS so that an output potential VADJ according to a potential difference (VMID−VREF) between the intermediate potential VMID and the reference potential VREF is output. More specifically, when the intermediate potential VMID is higher than the reference potential VREF, the output potential VADJ makes a transition toward the “H” level, and when the intermediate potential VMID is lower than the reference potential VREF, the output potential VADJ makes a transition toward the “L” level.
The voltage divider circuit 113 includes two resistors R11 and R12 connected in series to each other. One terminal of the voltage divider circuit 113 is connected to the drain of the output transistor QP11 and the other terminal is grounded. Moreover, a connection node of the resistors R11 and R12 is connected to an input terminal of the differential amplifier circuit 111. In this case, the voltage divider circuit 113 outputs the intermediate potential VMID, i.e., a voltage obtained by dividing the internal voltage VINT according to the ratio between respective resistance values of the resistors R1 and R2.
Thus, when the internal voltage VINT is reduced, the intermediate potential VMID becomes lower than the reference potential VREF and then the output voltage VADJ in the differential amplifier circuit 111 makes a transition toward the “L” level. Accordingly, the carrier supply amount of the output transistor QP11 is increased, so that reduction in the potential of the internal voltage VINT is suppressed. On the other hand, when the internal voltage VINT is increased, the intermediate potential VMID becomes higher than the reference potential VREF and then the output voltage VADJ in the differential amplifier circuit 111 makes a transition toward the “H” level. Accordingly, the carrier supply amount of the output transistor QP11 is reduced, so that increase in the potential of the internal voltage VINT is suppressed.
In this manner, the voltage reduction circuit 101 controls the output transistor QP11 using the differential amplifier circuit 111, so that change in the potential of the internal voltage VINT is suppressed, the internal voltage VINT as a stabilized voltage is generated from the power supply voltage VDD, and then the generated internal voltage VINT is supplied to the nonvolatile memory 103 serving as an internal circuit.
Moreover, in recent years, a semiconductor memory device in which a control circuit for receiving a control signal of the nonvolatile memory 103 to control the operation of the voltage reduction circuit 101 is provided to suppress reduction in the potential of the internal voltage VINT due to the operation of the nonvolatile memory 103 has been developed (see, e.g., Japanese Unexamined Patent Publication No. 5-21738). Hereinafter, as a second known example, the semiconductor memory device described in the publication will be described.
FIG. 9 is a block diagram illustrating the configuration of a semiconductor memory device according to a second known example. In FIG. 9, each member also shown in FIG. 8 is identified by the same reference numeral, and therefore, description thereof will be omitted.
As shown in FIG. 9, in the semiconductor memory device of the second known example, a p-channel compensating transistor QP12 which receives a control signal output by the control circuit 104 at the gate and of which source and drain are connected to the source and drain of the output transistor QP11, respectively, is provided.
To the control circuit 104, a nonvolatile memory driving signal NCE is input from the logic circuit 102. In this case, when the nonvolatile memory driving signal NCE makes a transition from the “H” level to the “L” level, the control circuit 104 is output the ground potential VSS during a predetermined period.
In the semiconductor memory device of the second known example, when a non-operation state of the nonvolatile memory 103 is changed to an operation state and the compensating transistor QP12 is turned ON, carriers are supplied from the power supply voltage VDD to the internal voltage VINT through the compensating transistor QP12. Thus, reduction in the potential of the internal voltage VINT is suppressed.
However, in the semiconductor memory device of the first known example, the internal voltage VINT rapidly falls when the nonvolatile memory 103 is in an operation state. Therefore, a problem might arise in operations of the logic circuit 102 and the nonvolatile memory 103.
Particularly, when the semiconductor memory device of the first known example is used for a non-contact IC card, a rapid fall of the internal voltage VINT stops the operation of the nonvolatile memory 103. More specifically, in the non-contact IC card, a power supply voltage VDD is supplied to a semiconductor device in the IC card by radio communication with a terminal called “reader/writer”. A voltage level of the power supply voltage VDD is largely changed according to a distance between the IC card and the reader/writer. Therefore, in many cases, a semiconductor memory device loaded in a non-contact IC card is so configured that when the internal voltage VINT becomes equal to or lower than a predetermined level by change in the power supply voltage VDD, the circuit operation of the nonvolatile memory 103 is stopped to protect data. Accordingly, a problem arises in which the operation of the nonvolatile memory is stopped when the internal voltage VINT rapidly falls.
To cope with this problem, in some cases, a capacitor with a large capacity is provided between the internal voltage VINT and the ground potential VSS. However, with this structure, a large area is necessary for forming a capacitor. Accordingly, reduction in a layout area for the semiconductor memory device becomes difficult.
Moreover, in the semiconductor memory device of the second known example, when the compensating transistor QP12 is turned ON, the power supply voltage VDD and the internal voltage VINT are directly connected to each other. Thus, an excess voltage might be applied to the nonvolatile memory 103. Therefore, the semiconductor memory device of the second known example is not practical in terms of reliability.
In this manner, both of the semiconductor memory devices of the first and second known examples have a problem in which when a non-operation state of the nonvolatile memory is changed to an operation state, it is difficult to suppress a rapid fall of the internal voltage.